GitHub

VHDL Asynchronous Reset Race Condition

This repository demonstrates a potential race condition in VHDL code involving an asynchronous reset and a rising-edge-triggered process. The buggy_counter.vhdl file contains the buggy code, while ...
GitHub

VHDL Counter: Race Condition or Asynchronous Assignment?

This repository demonstrates a potential issue in a VHDL counter implementation. The code appears straightforward, but subtle timing issues can lead to unexpected behavior. The core problem lies in ...
IEEE

VHDLASYN: A tool for synthesis of asynchronous systems from of VHDL behavioral specifications

Abstract: This paper presents a tool called VHDLASYN (VHDL Asynchronous SYNthesis) focused on synthesis of asynchronous digital systems. The tool employs the bundle-data decomposition design style ...