GitHub

Digital VLSI Design Lab: A collection of Verilog experiments implementing various modeling ...

This repository contains the lab experiments for ECE-5141 Digital VLSI Design Lab course, covering different modeling styles in Verilog HDL for VLSI circuit design.
GitHub

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

QiMeng-SALV introduces a novel framework for Verilog code generation that shifts reinforcement learning optimization from module-level to signal-level rewards. By leveraging AST analysis and ...